1. Field of the Invention
The present invention relates to a package structure, and more particularly, to a package structure that has an enhanced adhesion and airtight performance, a reduced usage of applied sealant and can prevent the active region from contamination.
2. Description of the Related Art
As the electronic devices, such as semiconductor devices, MicroElectroMechanical Systems (MEMS) devices and optoelectronic devices are becoming more and smaller, the circuitry therein used to drive these devices gets more compact accordingly. In order to isolate the devices from contamination such as dust, salt, grease or moisture to extend their lifespan and raise the reliability, the devices are required to be packaged so as to execute the functions of power distribution, signal distribution, heat dissipation, protection and support.
Most methods for packaging semiconductor devices are first to dice a wafer into dice and then package these dice into a variety of devices. In contrast, in the wafer-level package method, a wafer is packaged and tested before it is diced. Such a package method can reduce labor costs and shorten the time to make the semiconductor devices. Accordingly, this method is becoming more popular in the field of semiconductor package.
Referring to FIG. 1, it illustrates the cross-sectional view of a conventional electronic package 100. The package 100 includes a substrate 102 and an electronic device 106, such as MEMS device disposed on the active region 104 of the substrate 102. In order to effectively protect the electronic device 106 from malfunction caused by contamination such as dust or ambient atmosphere, and thus extend its lifespan and raise the reliability, a sealant 112 mixed with spacer balls 110 is applied to the surface of the substrate 102 and around the periphery of the active region 104. A substrate 108 such as a glass substrate is arranged over the electronic device 106 and pressed toward the substrate 102. The two substrates 102, 108 are bonded together via the sealant 112 and the spacer balls 110 dispersed in the sealant 112 can maintain a gap 114 between the two substrates 102, 108 for receiving the electronic device 106.
However, if the spacer balls 110 are of different size or non-uniformly dispersed in the sealant 112, the gap 114 between the two substrates 102, 108 is often non-uniform. The substrates 102, 108 may also be misaligned to each other if the applied force for bonding the substrates 102, 108 together is not uniform and thus cause the spacer balls 110 dispersed in the sealant 112 to roll or slide. Additionally, since the sealant 112 is flowable, the applied force can cause the sealant 112 to flow onto the active region 104 of the substrate 102 when the substrates 102, 108 are bonded together and thus the active region 104 is contaminated. Accordingly, the usage of the sealant 112, the applied force for bonding the substrates 102, 108 together, and the spacer balls 110 can significantly affect the area of the substrate 102 covered by the sealant 112, the gap between the substrates 102, 108, and the alignment of the substrates 102, 108 to each other.
In order to solve the above-mentioned problems, the U.S. Pat. No. 7,087,464 entitled “METHOD AND STRUCTURE FOR A WAFER LEVEL PACKAGING”, discloses a plurality of spacer walls formed on a semiconductor wafer or a transparent substrate by semiconductor process. The uniformity of the gap between the semiconductor wafer and the transparent substrate is controlled by these spacer walls. A sealant is applied to the inner sides or outer sides of the spacer walls so as to precisely control the position of the sealant. Accordingly, the distance between the sealant and active region can be significantly shortened and the width of the sealant can also be controlled. Although the method and structure disclosed in the Taiwan Patent Number 1222705 can effectively control the gap between two substrates and prevent the active region from contamination, the sealant is flowable and thus the amount of the sealant applied to the inner sides or outer sides of the spacer walls cannot be precisely controlled. Therefore, the usage of the sealant cannot be reduced, and the adhesion and airtight performance is still poor.
In view of the above, there exists a need to provide a package structure that has a uniform gap between two substrates and a good airtight seal so as to extend its lifespan and raise the reliability. Additionally, the package structure is required to be manufactured in the wafer-level package method in order to reduce the production cost.